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2 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF020
Not Recommended for New Designs
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25VF020. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions 1
Bus Cycle 2
1
2
3
4
5
Cycle
Type/Operation 3,4
S IN
S OUT
S IN
S OUT
S IN
S OUT
S IN
S OUT S IN
S OUT
Read
03H
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
X
D OUT
A 16
A 8
Sector-Erase 5,6
20H
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
-
-
A 16
A 8
Block-Erase 5,7
52H
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
-
-
A 16
A 8
Chip-Erase 6
Byte-Program 6
60H
02H
Hi-Z
Hi-Z
-
A 23 -
-
Hi-Z
-
A 15 -
-
Hi-Z
-
A 7 -A 0
-
Hi-Z
-
D I
-
Hi-Z
A 16
A 8
N
Auto Address Increment (AAI)
AFH
Hi-Z
A 23 -
Hi-Z
A 15 -
Hi-Z
A 7 -A 0
Hi-Z
D I
Hi-Z
Program 6,8
A 16
A 8
N
Read-Status-Register (RDSR)
05H
Hi-Z
X
D OU
-
Note
-
Note
-
Note 9
T
9
9
Enable-Write-Status-Register
50H
Hi-Z
-
-
-
-
-
-
-
-
(EWSR) 10
Write-Status-Register
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
(WRSR) 10
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
06H
04H
90H or
Hi-Z
Hi-Z
Hi-Z
-
-
00H
-
-
Hi-Z
-
-
00H
-
-
Hi-Z
-
-
ID
-
-
Hi-Z
-
-
X
-
-
D OUT
ABH
Addr 11
12
T5.0 25078
1. A MS = Most Significant Address
A MS = A 17 for SST25VF020
Address bits above the most significant bit of each density can be V IL or V IH
2. One bus cycle is eight clock periods.
3. Operation: S IN = Serial In, S OUT = Serial Out
4. X = Dummy Input Cycles (V IL or V IH ); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use A MS -A 12 , remaining addresses can be V IL or V IH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable
(WREN) instruction must be executed.
7. Block addresses for: use A MS -A 15 , remaining addresses can be V IL or V IH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
?2011 Silicon Storage Technology, Inc.
9
DS25078A
11/11
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